1. Field
Exemplary embodiments of the present invention relate to a memory device and a memory system including the same, and more particularly, to a repair-related technology.
2. Description of the Related Art
FIG. 1 is a diagram for explaining a repair operation in a typical memory device (for example, a DRAM).
FIG. 1 illustrates a configuration corresponding to one memory bank in a memory device. Referring to FIG. 1, the memory device includes a memory array 110 including a plurality of memory cells, a row circuit 120 for activating a word line selected by a row address R_ADD, and a column circuit 130 for accessing (reading or writing) data of a bit line selected by a column address.
A row fuse circuit 140 stores a row address which corresponds to a defective memory cell in the memory array 110, as a repair row address REPAIR_R_ADD. A row repair circuit 150 compares the repair row address REPAIR_R_ADD stored in the row fuse circuit 140 with a row address R_ADD inputted from the outside of the memory device. When the repair row address REPAIR_R_ADD coincides with the row address R_ADD, the row repair circuit 150 controls the row circuit 120 to activate a redundancy word line instead of a word line designated by the row address R_ADD. That is, a row (word line) corresponding to the repair row address REPAIR_R_ADD stored in the row fuse circuit 140 is replaced with a redundancy row (word line).
In FIG. 1, a signal RACT indicates a signal that is activated in response to an active command for activating a word line in the memory array 110, and deactivated in response to a precharge command for deactivating a word line. Furthermore, a signal RD indicates a read command and a signal WR indicates a write command.
In the row fuse circuit 140, a laser fuse is mainly used. The laser fuse stores ‘high’ or ‘low’ data according to whether the fuse has been cut. The laser fuse may be programmed in a wafer state, but it is not possible to program the laser fuse after a wafer is mounted in a package. It is difficult to design the laser fuse with a small area because there is a limitation in reducing a pitch thereof.
Therefore, as disclosed in U.S. Pat. Nos. 6,904,751, 6,777,757, 6,667,902, 7,173,851, and 7,269,047, one of nonvolatile memories, such as an E-fuse array circuit, a NAND flash memory, a NOR flash memory, a MRAM (Magnetic Random Access Memory), a STT-MRAM (Spin Transfer Torque-Magnetic Random Access Memory), a ReRAM (Resistive Random Access Memory), or a PCRAM (Phase Change. Random Access Memory), is included into a memory device, and repair information (repair addresses) is stored in the nonvolatile memory for use.
FIG. 2 is a diagram illustrating an example in which a nonvolatile memory is used in a memory device in order to store repair information.
Referring to FIG. 2, the memory device includes a plurality of memory banks BK0 to BK3, registers 210_0 to 210_3 provided to the respective memory banks BK0 to BK3 to store repair information, and a nonvolatile memory 201.
The nonvolatile memory 201 is a substitution for the fuse circuit 140. The nonvolatile memory 201 stores repair information corresponding to all the banks BK0 to BK3, that is, repair addresses. The nonvolatile memory may include one of nonvolatile memories, such as an E-fuse array circuit, a NAND flash memory, a NOR flash memory a MRAM (Magnetic. Random. Access Memory), a STT-MRAM (Spin Transfer Torque-Magnetic Random Access Memory), a ReRAM (Resistive Random Access Memory), or a PCRAM (Phase Change Random Access Memory).
The registers 210_0 to 210_3 provided to the respective memory banks BK0 to BK3 store repair information of the corresponding memory bank. The register 210_0 stores repair information of the memory bank BK0, and the register 210_2 stores repair information of the memory bank BK2. Each of the registers 210_0 to 210_3 includes a latch circuit and is able to store repair information only when power is being supplied thereto. The repair information to be stored in the registers 210_0 to 210_3 is received from the nonvolatile memory 201.
The reason why the repair information stored in the nonvolatile memory 201 is not directly used but stored in the registers 210_0 to 210_3 and then used, is as follows. Since the nonvolatile memory 201 has an array structure, it takes a predetermined time to call data stored therein. Since it is difficult to immediately call data, a repair operation may not be performed properly by directly using data stored in the nonvolatile memory 201. Accordingly, a boot-up operation is performed to transmit the repair information stored in the nonvolatile memory 201 to the registers 210_0 to 210_3 for storage, and a repair operation is performed using the data stored in the registers 210_0 to 210_3 after the boot-up operation is performed.
In the case of replacing the fuse circuit 140 including a laser fuse with the nonvolatile memory 201 and the registers 210_0 to 210_3, additional defects may be found and repaired after a wafer state. There has been conducted research on a technology capable of checking the nonvolatile memory 201 and repairing checked defects thereof even after a memory device is fabricated (for example, even after a product is sold).